🔬 LAYER 01
01. Semiconductor & Physical Infrastructure The physical hardware foundation and semiconductor supply chain powering modern AI, spanning silicon microarchitecture, EDA & verification, wafer fabrication & equipment, advanced packaging & HBM, and server systems engineering.
🔄 Sub-Domain Sequential Path (5 stages):
1.1
1.1 Compute Silicon Architecture & Custom Accelerators Open Sub-Page ➔ GPU, CPU, TPU, NPU, custom ASIC, SoC, chiplet architecture, tensor/matrix engines, cache hierarchies, NoC interconnects, and heterogeneous compute.
GPU Microarchitecture & Parallel Compute Cores Streaming multiprocessors (NVIDIA SM / AMD CU / Intel Xe Core), matrix engines (Tensor Core / Matrix Core), FP8/FP4/INT4 micro-op execution, warp/wavefront schedulers, and high-bandwidth on-chip SRAM.
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GPU Tensor Core SM / CU Warp Scheduling SRAM Heterogeneous Compute FP8/FP4 Precision NoC
💼 Roles & Salary
CPU/GPU/AI Accelerator Architect、Microarchitecture Engineer、RTL Design Engineer、Performance Modeling Engineer
💰 $220K - $480K / year (Silicon Valley Base+Equity) | ¥600K - ¥1.6M / year (China HQ)
⚡ 【Mini-Sandbox】FlashAttention Memory Savings
Naive Attention
1,024 MB
O(N²) 显存暴涨
FlashAttention
32 MB
节省 97% 显存 (O(N))
Domain-Specific AI Accelerators & Custom ASIC Google TPU (Systolic Arrays), AWS Trainium/Inferentia, Groq TSP (deterministic streaming), Cerebras Wafer-Scale Engine, and custom low-power edge/cloud ASIC accelerators.
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TPU NPU Custom ASIC Systolic Array Spatial Architecture AI Accelerators Chiplet SoC
💼 Roles & Salary
ASIC Design Engineer、SoC Architect、Design Verification Engineer、AI Compiler Engineer
💰 $200K - $440K / year (ASIC Design Track) | ¥500K - ¥1.4M / year
⬇
EDA toolchains, Silicon IP cores (CPU/SerDes/NoC/D2D), logic synthesis, DFT/ATPG, formal verification, STA signoff, physical design, and multiphysics simulation.
EDA Automation, Physical Design & Signoff Logic synthesis, automated place & route (P&R), static timing analysis (STA), IR drop & electromigration analysis, DRC/LVS physical signoff, and PDK enablement.
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EDA Synthesis Place & Route STA DRC/LVS IR Drop PDK Signoff
💼 Roles & Salary
Physical Design Engineer、Timing/Signoff Engineer、EDA Software Engineer、PDK Engineer、CAD Flow Engineer
💰 $180K - $390K / year (EDA / Physical Design) | ¥450K - ¥1.2M / year
Silicon IP, Frontend Verification & Multiphysics High-speed SerDes/D2D interface IP, ARM/RISC-V CPU IP, UVM testbenches, formal property verification (SVA), DFT/ATPG scan insertion, and SI/PI electromagnetic/thermal multiphysics co-simulation.
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Silicon IP SerDes IP UVM Formal Verification DFT ATPG SI/PI Multiphysics Simulation
💼 Roles & Salary
Design Verification Engineer、Formal Verification Engineer、DFT Engineer、SI/PI Engineer
💰 $190K - $410K / year (Silicon IP & DV) | ¥500K - ¥1.3M / year
⬇
1.3
1.3 Semiconductor Equipment, Fabrication & Process Control Open Sub-Page ➔ Foundry wafer manufacturing, EUV/DUV lithography, GAAFET/Nanosheet sub-3nm process integration, thin-film deposition, plasma etch, metrology, and wafer yield control.
Advanced Foundry & Process Integration Sub-3nm/2nm advanced process nodes, Extreme Ultraviolet (EUV / High-NA EUV) lithography, Gate-All-Around (GAAFET/Nanosheet) transistors, Backside Power Delivery (BSPDN), and defect-driven wafer yield optimization.
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Foundry EUV GAAFET Nanosheet BSPDN Process Integration Wafer Yield SPC/DOE
💼 Roles & Salary
Process Integration Engineer、Process Development Engineer、Yield Engineer
💰 $170K - $360K / year (Foundry PIE & Process) | ¥400K - ¥950K / year
Semiconductor Equipment & Metrology Process Control EUV lithography scanners, atomic layer deposition (ALD), high-density plasma etch, chemical-mechanical planarization (CMP), and optical/e-beam wafer defect inspection & CD-SEM metrology systems.
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ASML EUV ALD Plasma Etch CMP Metrology Defect Inspection CD-SEM Yield Management
💼 Roles & Salary
Equipment Engineer、Lithography/OPC Engineer、Metrology Engineer
💰 $175K - $370K / year (Equipment & Metrology) | ¥420K - ¥1.0M / year
⬇
CoWoS, SoIC, 2.5D/3D wafer-level packaging, Chiplet heterogeneous interconnects (UCIe), HBM3e/HBM4 high-bandwidth memory, DDR5 controllers, and high-density packaging yield.
Advanced Packaging & Chiplet Integration Overcoming reticle limits: TSMC CoWoS / SoIC, Intel EMIB / Foveros, silicon interposers, through-silicon vias (TSV), micro-bumps & hybrid bonding, UCIe die-to-die standard, and advanced OSAT assembly.
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CoWoS Chiplet 2.5D/3D Packaging TSV Hybrid Bonding UCIe Interposer OSAT
💼 Roles & Salary
Package Design Engineer、Chiplet Integration Engineer、Packaging Process Engineer、SI/PI Engineer
💰 $195K - $420K / year (Advanced Packaging & Chiplets) | ¥480K - ¥1.25M / year
HBM & High-Speed Memory Subsystems Conquering LLM training & inference memory walls: HBM3e/HBM4 3D DRAM die stacks, 1024-bit+ ultra-wide channels, MR-DIMM/CXL memory expansion, and high-performance memory controllers & PHYs.
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HBM3e HBM4 Memory Wall DDR5 / LPDDR5X Memory Controller CXL Memory Bandwidth ECC
💼 Roles & Salary
Memory Architect、HBM Design Engineer、Memory Controller Engineer
💰 $210K - $450K / year (HBM & Memory Arch) | ¥550K - ¥1.45M / year
⬇
AI server architectures, GPU compute trays, OAM/UBB/MGX module standards, BMC/Redfish firmware, high-efficiency power delivery (PSU/PDU/Busbar), and direct-to-chip & immersion liquid cooling.
AI Server Systems & Hardware Architecture 8-GPU compute trays, rack-scale modular systems (OAM/UBB, MGX), PCIe Gen5/CXL high-speed baseboards, OpenBMC/Redfish management firmware, and hardware reliability testing.
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AI Server Compute Tray OAM / UBB MGX PCIe Gen5 / CXL OpenBMC Hardware Bring-up
💼 Roles & Salary
Server Hardware Engineer、Rack Systems Architect、Board/PCB Design Engineer、BMC/Firmware Engineer
💰 $170K - $360K / year (AI Server Systems) | ¥380K - ¥900K / year
High-Density Power Delivery & Liquid Cooling 100kW+ rack direct-to-chip microchannel cold plates, Coolant Distribution Units (CDU), secondary manifolds, 48V/HVDC busbars, titanium-grade PSU/PDU, and thermo-fluid CFD simulations.
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Direct-to-Chip Cold Plate CDU Liquid Cooling HVDC Busbar PDU / PSU CFD Thermal Simulation
💼 Roles & Salary
Power Electronics Engineer、Thermal Engineer、Liquid Cooling Engineer
💰 $165K - $350K / year (Power & Liquid Cooling) | ¥360K - ¥850K / year