01. Semiconductor & Physical Infrastructure
The physical hardware foundation and semiconductor supply chain powering modern AI, spanning silicon microarchitecture, EDA & verification, wafer fabrication & equipment, advanced packaging & HBM, and server systems engineering.
1.1 Compute Silicon Architecture & Custom Accelerators
GPU, CPU, TPU, NPU, custom ASIC, SoC, chiplet architecture, tensor/matrix engines, cache hierarchies, NoC interconnects, and heterogeneous compute.
GPU Microarchitecture & Parallel Compute Cores
Streaming multiprocessors (NVIDIA SM / AMD CU / Intel Xe Core), matrix engines (Tensor Core / Matrix Core), FP8/FP4/INT4 micro-op execution, warp/wavefront schedulers, and high-bandwidth on-chip SRAM.
Domain-Specific AI Accelerators & Custom ASIC
Google TPU (Systolic Arrays), AWS Trainium/Inferentia, Groq TSP (deterministic streaming), Cerebras Wafer-Scale Engine, and custom low-power edge/cloud ASIC accelerators.
1.2 Silicon IP, EDA & Design Verification
EDA toolchains, Silicon IP cores (CPU/SerDes/NoC/D2D), logic synthesis, DFT/ATPG, formal verification, STA signoff, physical design, and multiphysics simulation.
EDA Automation, Physical Design & Signoff
Logic synthesis, automated place & route (P&R), static timing analysis (STA), IR drop & electromigration analysis, DRC/LVS physical signoff, and PDK enablement.
Silicon IP, Frontend Verification & Multiphysics
High-speed SerDes/D2D interface IP, ARM/RISC-V CPU IP, UVM testbenches, formal property verification (SVA), DFT/ATPG scan insertion, and SI/PI electromagnetic/thermal multiphysics co-simulation.
1.3 Semiconductor Equipment, Fabrication & Process Control
Foundry wafer manufacturing, EUV/DUV lithography, GAAFET/Nanosheet sub-3nm process integration, thin-film deposition, plasma etch, metrology, and wafer yield control.
Advanced Foundry & Process Integration
Sub-3nm/2nm advanced process nodes, Extreme Ultraviolet (EUV / High-NA EUV) lithography, Gate-All-Around (GAAFET/Nanosheet) transistors, Backside Power Delivery (BSPDN), and defect-driven wafer yield optimization.
Semiconductor Equipment & Metrology Process Control
EUV lithography scanners, atomic layer deposition (ALD), high-density plasma etch, chemical-mechanical planarization (CMP), and optical/e-beam wafer defect inspection & CD-SEM metrology systems.
1.4 Advanced Packaging, Chiplets & High-Speed Memory
CoWoS, SoIC, 2.5D/3D wafer-level packaging, Chiplet heterogeneous interconnects (UCIe), HBM3e/HBM4 high-bandwidth memory, DDR5 controllers, and high-density packaging yield.
Advanced Packaging & Chiplet Integration
Overcoming reticle limits: TSMC CoWoS / SoIC, Intel EMIB / Foveros, silicon interposers, through-silicon vias (TSV), micro-bumps & hybrid bonding, UCIe die-to-die standard, and advanced OSAT assembly.
HBM & High-Speed Memory Subsystems
Conquering LLM training & inference memory walls: HBM3e/HBM4 3D DRAM die stacks, 1024-bit+ ultra-wide channels, MR-DIMM/CXL memory expansion, and high-performance memory controllers & PHYs.
1.5 AI Server Hardware, Power & Cooling
AI server architectures, GPU compute trays, OAM/UBB/MGX module standards, BMC/Redfish firmware, high-efficiency power delivery (PSU/PDU/Busbar), and direct-to-chip & immersion liquid cooling.
AI Server Systems & Hardware Architecture
8-GPU compute trays, rack-scale modular systems (OAM/UBB, MGX), PCIe Gen5/CXL high-speed baseboards, OpenBMC/Redfish management firmware, and hardware reliability testing.
High-Density Power Delivery & Liquid Cooling
100kW+ rack direct-to-chip microchannel cold plates, Coolant Distribution Units (CDU), secondary manifolds, 48V/HVDC busbars, titanium-grade PSU/PDU, and thermo-fluid CFD simulations.