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LAYER 01

01. Semiconductor & Physical Infrastructure

Benchmark Companies:
NVIDIANVIDIATSMCTSMCASMLASMLAMDAMDIntelIntelQualcommQualcommArmArmBroadcomBroadcomMarvellMarvellSK HynixSK HynixSamsungSamsungMicronMicronSynopsysSynopsysCadenceCadenceSiemens EDASiemens EDAApplied MaterialsApplied MaterialsLam ResearchLam ResearchTokyo ElectronTokyo ElectronKLAKLAOnto InnovationOnto InnovationASE GroupASE GroupAmkor TechnologyAmkor TechnologyJCET (长电科技)JCET (长电科技)SupermicroSupermicroDellDellHPEHPEFoxconnFoxconnVertivVertivSchneider ElectricSchneider ElectricEatonEatonDelta ElectronicsDelta ElectronicsGoogle CloudGoogle CloudAWSAWSGroqGroqTenstorrentTenstorrentCerebrasCerebrasRambusRambusSiFiveSiFiveSamsung FoundrySamsung FoundryIntel FoundryIntel FoundryLenovoLenovoQuanta / QCTQuanta / QCTWiwynnWiwynnCoolIT SystemsCoolIT Systems

The physical hardware foundation and semiconductor supply chain powering modern AI, spanning silicon microarchitecture, EDA & verification, wafer fabrication & equipment, advanced packaging & HBM, and server systems engineering.

📊Layer View Mode:
🌐3D CROSS-CORRELATION MATRIX

01. Semiconductor & Physical Infrastructure · Cross-Correlation Ecosystem

Click any company, tech category, or career role to illuminate all cross-associations and dim unrelated entities.

🔍
🏢

Benchmark Enterprises

44
NVIDIANVIDIA
1
TSMCTSMC
2
ASMLASML
1
AMDAMD
1
IntelIntel
3
QualcommQualcomm
2
ArmArm
3
BroadcomBroadcom
1
MarvellMarvell
1
SK HynixSK Hynix
1
SamsungSamsung
3
MicronMicron
1
SynopsysSynopsys
2
CadenceCadence
2
Siemens EDASiemens EDA
2
Applied MaterialsApplied Materials
1
Lam ResearchLam Research
1
Tokyo ElectronTokyo Electron
1
KLAKLA
1
Onto InnovationOnto Innovation
1
ASE GroupASE Group
1
Amkor TechnologyAmkor Technology
1
JCET (长电科技)JCET (长电科技)
1
SupermicroSupermicro
2
DellDell
1
HPEHPE
1
FoxconnFoxconn
1
VertivVertiv
1
Schneider ElectricSchneider Electric
1
EatonEaton
1
Delta ElectronicsDelta Electronics
1
Google CloudGoogle Cloud
1
AWSAWS
1
GroqGroq
1
TenstorrentTenstorrent
1
CerebrasCerebras
1
RambusRambus
2
SiFiveSiFive
1
Samsung FoundrySamsung Foundry
3
Intel FoundryIntel Foundry
3
LenovoLenovo
1
Quanta / QCTQuanta / QCT
1
WiwynnWiwynn
1
CoolIT SystemsCoolIT Systems
1
🛠️

Tech Stack Categories & Atomic Nodes

5 Tracks
1.1

1.1 Compute Silicon Architecture & Custom Accelerators

GPU, CPU, TPU, NPU, custom ASIC, SoC, chiplet architecture, tensor/matrix engines, cache hierarchies, NoC interconnects, and heterogeneous compute.
Sub-Page
GPU Microarchitecture & Parallel Compute Cores
💰 $220K - $480K / year (Silicon Valley Base+Equity) | ¥600K - ¥1.6M / year (China HQ)
Streaming multiprocessors (NVIDIA SM / AMD CU / Intel Xe Core), matrix engines (Tensor Core / Matrix Core), FP8/FP4/INT4 micro-op execution, warp/wavefront schedulers, and high-bandwidth on-chip SRAM.
Benchmark:NVIDIANVIDIAAMDAMDIntelIntelArmArmQualcommQualcomm
GPUTensor CoreSM / CUWarp SchedulingSRAMHeterogeneous ComputeFP8/FP4 PrecisionNoC
Domain-Specific AI Accelerators & Custom ASIC
💰 $200K - $440K / year (ASIC Design Track) | ¥500K - ¥1.4M / year
Google TPU (Systolic Arrays), AWS Trainium/Inferentia, Groq TSP (deterministic streaming), Cerebras Wafer-Scale Engine, and custom low-power edge/cloud ASIC accelerators.
Benchmark:Google CloudGoogle CloudAWSAWSBroadcomBroadcomMarvellMarvellGroqGroqTenstorrentTenstorrentCerebrasCerebrasQualcommQualcommArmArm
TPUNPUCustom ASICSystolic ArraySpatial ArchitectureAI AcceleratorsChipletSoC
1.2

1.2 Silicon IP, EDA & Design Verification

EDA toolchains, Silicon IP cores (CPU/SerDes/NoC/D2D), logic synthesis, DFT/ATPG, formal verification, STA signoff, physical design, and multiphysics simulation.
Sub-Page
EDA Automation, Physical Design & Signoff
💰 $180K - $390K / year (EDA / Physical Design) | ¥450K - ¥1.2M / year
Logic synthesis, automated place & route (P&R), static timing analysis (STA), IR drop & electromigration analysis, DRC/LVS physical signoff, and PDK enablement.
Benchmark:SynopsysSynopsysCadenceCadenceSiemens EDASiemens EDA
EDASynthesisPlace & RouteSTADRC/LVSIR DropPDKSignoff
Silicon IP, Frontend Verification & Multiphysics
💰 $190K - $410K / year (Silicon IP & DV) | ¥500K - ¥1.3M / year
High-speed SerDes/D2D interface IP, ARM/RISC-V CPU IP, UVM testbenches, formal property verification (SVA), DFT/ATPG scan insertion, and SI/PI electromagnetic/thermal multiphysics co-simulation.
Benchmark:ArmArmSynopsysSynopsysCadenceCadenceRambusRambusSiFiveSiFiveSiemens EDASiemens EDA
Silicon IPSerDes IPUVMFormal VerificationDFTATPGSI/PIMultiphysics Simulation
1.3

1.3 Semiconductor Equipment, Fabrication & Process Control

Foundry wafer manufacturing, EUV/DUV lithography, GAAFET/Nanosheet sub-3nm process integration, thin-film deposition, plasma etch, metrology, and wafer yield control.
Sub-Page
Advanced Foundry & Process Integration
💰 $170K - $360K / year (Foundry PIE & Process) | ¥400K - ¥950K / year
Sub-3nm/2nm advanced process nodes, Extreme Ultraviolet (EUV / High-NA EUV) lithography, Gate-All-Around (GAAFET/Nanosheet) transistors, Backside Power Delivery (BSPDN), and defect-driven wafer yield optimization.
Benchmark:TSMCTSMCSamsung FoundrySamsung FoundryIntel FoundryIntel Foundry
FoundryEUVGAAFETNanosheetBSPDNProcess IntegrationWafer YieldSPC/DOE
Semiconductor Equipment & Metrology Process Control
💰 $175K - $370K / year (Equipment & Metrology) | ¥420K - ¥1.0M / year
EUV lithography scanners, atomic layer deposition (ALD), high-density plasma etch, chemical-mechanical planarization (CMP), and optical/e-beam wafer defect inspection & CD-SEM metrology systems.
Benchmark:ASMLASMLApplied MaterialsApplied MaterialsLam ResearchLam ResearchTokyo ElectronTokyo ElectronKLAKLAOnto InnovationOnto Innovation
ASML EUVALDPlasma EtchCMPMetrologyDefect InspectionCD-SEMYield Management
1.4

1.4 Advanced Packaging, Chiplets & High-Speed Memory

CoWoS, SoIC, 2.5D/3D wafer-level packaging, Chiplet heterogeneous interconnects (UCIe), HBM3e/HBM4 high-bandwidth memory, DDR5 controllers, and high-density packaging yield.
Sub-Page
Advanced Packaging & Chiplet Integration
💰 $195K - $420K / year (Advanced Packaging & Chiplets) | ¥480K - ¥1.25M / year
Overcoming reticle limits: TSMC CoWoS / SoIC, Intel EMIB / Foveros, silicon interposers, through-silicon vias (TSV), micro-bumps & hybrid bonding, UCIe die-to-die standard, and advanced OSAT assembly.
Benchmark:TSMCTSMCIntelIntelSamsungSamsungASE GroupASE GroupAmkor TechnologyAmkor TechnologyJCET (长电科技)JCET (长电科技)
CoWoSChiplet2.5D/3D PackagingTSVHybrid BondingUCIeInterposerOSAT
HBM & High-Speed Memory Subsystems
💰 $210K - $450K / year (HBM & Memory Arch) | ¥550K - ¥1.45M / year
Conquering LLM training & inference memory walls: HBM3e/HBM4 3D DRAM die stacks, 1024-bit+ ultra-wide channels, MR-DIMM/CXL memory expansion, and high-performance memory controllers & PHYs.
Benchmark:SK HynixSK HynixSamsungSamsungMicronMicronRambusRambus
HBM3eHBM4Memory WallDDR5 / LPDDR5XMemory ControllerCXLMemory BandwidthECC
1.5

1.5 AI Server Hardware, Power & Cooling

AI server architectures, GPU compute trays, OAM/UBB/MGX module standards, BMC/Redfish firmware, high-efficiency power delivery (PSU/PDU/Busbar), and direct-to-chip & immersion liquid cooling.
Sub-Page
AI Server Systems & Hardware Architecture
💰 $170K - $360K / year (AI Server Systems) | ¥380K - ¥900K / year
8-GPU compute trays, rack-scale modular systems (OAM/UBB, MGX), PCIe Gen5/CXL high-speed baseboards, OpenBMC/Redfish management firmware, and hardware reliability testing.
Benchmark:SupermicroSupermicroDellDellHPEHPELenovoLenovoQuanta / QCTQuanta / QCTWiwynnWiwynnFoxconnFoxconn
AI ServerCompute TrayOAM / UBBMGXPCIe Gen5 / CXLOpenBMCHardware Bring-up
High-Density Power Delivery & Liquid Cooling
💰 $165K - $350K / year (Power & Liquid Cooling) | ¥360K - ¥850K / year
100kW+ rack direct-to-chip microchannel cold plates, Coolant Distribution Units (CDU), secondary manifolds, 48V/HVDC busbars, titanium-grade PSU/PDU, and thermo-fluid CFD simulations.
Benchmark:VertivVertivSchneider ElectricSchneider ElectricEatonEatonDelta ElectronicsDelta ElectronicsCoolIT SystemsCoolIT SystemsSupermicroSupermicro
Direct-to-ChipCold PlateCDULiquid CoolingHVDC BusbarPDU / PSUCFD Thermal Simulation
💼

Career Track Roles

35
💼CPU/GPU/AI Accelerator Architect
1
💼Microarchitecture Engineer
1
💼RTL Design Engineer
1
💼ASIC Design Engineer
1
💼Design Verification Engineer
2
💼Formal Verification Engineer
1
💼Performance Modeling Engineer
1
💼AI Compiler Engineer
1
💼Physical Design Engineer
1
💼Timing/Signoff Engineer
1
💼EDA Software Engineer
1
💼PDK Engineer
1
💼SI/PI Engineer
2
💼Process Integration Engineer
1
💼Process Development Engineer
1
💼Lithography/OPC Engineer
1
💼Equipment Engineer
1
💼Yield Engineer
1
💼Package Design Engineer
1
💼Packaging Process Engineer
1
💼Chiplet Integration Engineer
1
💼Memory Architect
1
💼HBM Design Engineer
1
💼Memory Controller Engineer
1
💼Server Hardware Engineer
1
💼Rack Systems Architect
1
💼Board/PCB Design Engineer
1
💼BMC/Firmware Engineer
1
💼Power Electronics Engineer
1
💼Thermal Engineer
1
💼Liquid Cooling Engineer
1
💼SoC Architect
1
💼CAD Flow Engineer
1
💼DFT Engineer
1
💼Metrology Engineer
1
🔄Sub-Domain Sequential Path (5 stages):
1.1

1.1 Compute Silicon Architecture & Custom Accelerators

Open Sub-Page

GPU, CPU, TPU, NPU, custom ASIC, SoC, chiplet architecture, tensor/matrix engines, cache hierarchies, NoC interconnects, and heterogeneous compute.

GPU Microarchitecture & Parallel Compute Cores

Streaming multiprocessors (NVIDIA SM / AMD CU / Intel Xe Core), matrix engines (Tensor Core / Matrix Core), FP8/FP4/INT4 micro-op execution, warp/wavefront schedulers, and high-bandwidth on-chip SRAM.

🏢 Companies
NVIDIANVIDIAAMDAMDIntelIntelArmArmQualcommQualcomm
🛠️ Tech Stack
GPUTensor CoreSM / CUWarp SchedulingSRAMHeterogeneous ComputeFP8/FP4 PrecisionNoC
💼 Roles & Salary
CPU/GPU/AI Accelerator Architect、Microarchitecture Engineer、RTL Design Engineer、Performance Modeling Engineer
💰 $220K - $480K / year (Silicon Valley Base+Equity) | ¥600K - ¥1.6M / year (China HQ)
【Mini-Sandbox】FlashAttention Memory Savings
Sequence Length:4,096 tokens
Naive Attention
1,024 MB
O(N²) 显存暴涨
FlashAttention
32 MB
节省 97% 显存 (O(N))

Domain-Specific AI Accelerators & Custom ASIC

Google TPU (Systolic Arrays), AWS Trainium/Inferentia, Groq TSP (deterministic streaming), Cerebras Wafer-Scale Engine, and custom low-power edge/cloud ASIC accelerators.

🏢 Companies
Google CloudGoogle CloudAWSAWSBroadcomBroadcomMarvellMarvellGroqGroqTenstorrentTenstorrentCerebrasCerebrasQualcommQualcommArmArm
🛠️ Tech Stack
TPUNPUCustom ASICSystolic ArraySpatial ArchitectureAI AcceleratorsChipletSoC
💼 Roles & Salary
ASIC Design Engineer、SoC Architect、Design Verification Engineer、AI Compiler Engineer
💰 $200K - $440K / year (ASIC Design Track) | ¥500K - ¥1.4M / year
1.2

1.2 Silicon IP, EDA & Design Verification

Open Sub-Page

EDA toolchains, Silicon IP cores (CPU/SerDes/NoC/D2D), logic synthesis, DFT/ATPG, formal verification, STA signoff, physical design, and multiphysics simulation.

EDA Automation, Physical Design & Signoff

Logic synthesis, automated place & route (P&R), static timing analysis (STA), IR drop & electromigration analysis, DRC/LVS physical signoff, and PDK enablement.

🏢 Companies
SynopsysSynopsysCadenceCadenceSiemens EDASiemens EDA
🛠️ Tech Stack
EDASynthesisPlace & RouteSTADRC/LVSIR DropPDKSignoff
💼 Roles & Salary
Physical Design Engineer、Timing/Signoff Engineer、EDA Software Engineer、PDK Engineer、CAD Flow Engineer
💰 $180K - $390K / year (EDA / Physical Design) | ¥450K - ¥1.2M / year

Silicon IP, Frontend Verification & Multiphysics

High-speed SerDes/D2D interface IP, ARM/RISC-V CPU IP, UVM testbenches, formal property verification (SVA), DFT/ATPG scan insertion, and SI/PI electromagnetic/thermal multiphysics co-simulation.

🏢 Companies
ArmArmSynopsysSynopsysCadenceCadenceRambusRambusSiFiveSiFiveSiemens EDASiemens EDA
🛠️ Tech Stack
Silicon IPSerDes IPUVMFormal VerificationDFTATPGSI/PIMultiphysics Simulation
💼 Roles & Salary
Design Verification Engineer、Formal Verification Engineer、DFT Engineer、SI/PI Engineer
💰 $190K - $410K / year (Silicon IP & DV) | ¥500K - ¥1.3M / year
1.3

1.3 Semiconductor Equipment, Fabrication & Process Control

Open Sub-Page

Foundry wafer manufacturing, EUV/DUV lithography, GAAFET/Nanosheet sub-3nm process integration, thin-film deposition, plasma etch, metrology, and wafer yield control.

Advanced Foundry & Process Integration

Sub-3nm/2nm advanced process nodes, Extreme Ultraviolet (EUV / High-NA EUV) lithography, Gate-All-Around (GAAFET/Nanosheet) transistors, Backside Power Delivery (BSPDN), and defect-driven wafer yield optimization.

🏢 Companies
TSMCTSMCSamsung FoundrySamsung FoundryIntel FoundryIntel Foundry
🛠️ Tech Stack
FoundryEUVGAAFETNanosheetBSPDNProcess IntegrationWafer YieldSPC/DOE
💼 Roles & Salary
Process Integration Engineer、Process Development Engineer、Yield Engineer
💰 $170K - $360K / year (Foundry PIE & Process) | ¥400K - ¥950K / year

Semiconductor Equipment & Metrology Process Control

EUV lithography scanners, atomic layer deposition (ALD), high-density plasma etch, chemical-mechanical planarization (CMP), and optical/e-beam wafer defect inspection & CD-SEM metrology systems.

🏢 Companies
ASMLASMLApplied MaterialsApplied MaterialsLam ResearchLam ResearchTokyo ElectronTokyo ElectronKLAKLAOnto InnovationOnto Innovation
🛠️ Tech Stack
ASML EUVALDPlasma EtchCMPMetrologyDefect InspectionCD-SEMYield Management
💼 Roles & Salary
Equipment Engineer、Lithography/OPC Engineer、Metrology Engineer
💰 $175K - $370K / year (Equipment & Metrology) | ¥420K - ¥1.0M / year
1.4

1.4 Advanced Packaging, Chiplets & High-Speed Memory

Open Sub-Page

CoWoS, SoIC, 2.5D/3D wafer-level packaging, Chiplet heterogeneous interconnects (UCIe), HBM3e/HBM4 high-bandwidth memory, DDR5 controllers, and high-density packaging yield.

Advanced Packaging & Chiplet Integration

Overcoming reticle limits: TSMC CoWoS / SoIC, Intel EMIB / Foveros, silicon interposers, through-silicon vias (TSV), micro-bumps & hybrid bonding, UCIe die-to-die standard, and advanced OSAT assembly.

🏢 Companies
TSMCTSMCIntelIntelSamsungSamsungASE GroupASE GroupAmkor TechnologyAmkor TechnologyJCET (长电科技)JCET (长电科技)
🛠️ Tech Stack
CoWoSChiplet2.5D/3D PackagingTSVHybrid BondingUCIeInterposerOSAT
💼 Roles & Salary
Package Design Engineer、Chiplet Integration Engineer、Packaging Process Engineer、SI/PI Engineer
💰 $195K - $420K / year (Advanced Packaging & Chiplets) | ¥480K - ¥1.25M / year

HBM & High-Speed Memory Subsystems

Conquering LLM training & inference memory walls: HBM3e/HBM4 3D DRAM die stacks, 1024-bit+ ultra-wide channels, MR-DIMM/CXL memory expansion, and high-performance memory controllers & PHYs.

🏢 Companies
SK HynixSK HynixSamsungSamsungMicronMicronRambusRambus
🛠️ Tech Stack
HBM3eHBM4Memory WallDDR5 / LPDDR5XMemory ControllerCXLMemory BandwidthECC
💼 Roles & Salary
Memory Architect、HBM Design Engineer、Memory Controller Engineer
💰 $210K - $450K / year (HBM & Memory Arch) | ¥550K - ¥1.45M / year
1.5

1.5 AI Server Hardware, Power & Cooling

Open Sub-Page

AI server architectures, GPU compute trays, OAM/UBB/MGX module standards, BMC/Redfish firmware, high-efficiency power delivery (PSU/PDU/Busbar), and direct-to-chip & immersion liquid cooling.

AI Server Systems & Hardware Architecture

8-GPU compute trays, rack-scale modular systems (OAM/UBB, MGX), PCIe Gen5/CXL high-speed baseboards, OpenBMC/Redfish management firmware, and hardware reliability testing.

🏢 Companies
SupermicroSupermicroDellDellHPEHPELenovoLenovoQuanta / QCTQuanta / QCTWiwynnWiwynnFoxconnFoxconn
🛠️ Tech Stack
AI ServerCompute TrayOAM / UBBMGXPCIe Gen5 / CXLOpenBMCHardware Bring-up
💼 Roles & Salary
Server Hardware Engineer、Rack Systems Architect、Board/PCB Design Engineer、BMC/Firmware Engineer
💰 $170K - $360K / year (AI Server Systems) | ¥380K - ¥900K / year

High-Density Power Delivery & Liquid Cooling

100kW+ rack direct-to-chip microchannel cold plates, Coolant Distribution Units (CDU), secondary manifolds, 48V/HVDC busbars, titanium-grade PSU/PDU, and thermo-fluid CFD simulations.

🏢 Companies
VertivVertivSchneider ElectricSchneider ElectricEatonEatonDelta ElectronicsDelta ElectronicsCoolIT SystemsCoolIT SystemsSupermicroSupermicro
🛠️ Tech Stack
Direct-to-ChipCold PlateCDULiquid CoolingHVDC BusbarPDU / PSUCFD Thermal Simulation
💼 Roles & Salary
Power Electronics Engineer、Thermal Engineer、Liquid Cooling Engineer
💰 $165K - $350K / year (Power & Liquid Cooling) | ¥360K - ¥850K / year