1.2
1.2 Silicon IP, EDA & Design Verification
EDA toolchains, Silicon IP cores (CPU/SerDes/NoC/D2D), logic synthesis, DFT/ATPG, formal verification, STA signoff, physical design, and multiphysics simulation.
EDA Automation, Physical Design & Signoff
Logic synthesis, automated place & route (P&R), static timing analysis (STA), IR drop & electromigration analysis, DRC/LVS physical signoff, and PDK enablement.
🏢 Companies
Synopsys、Cadence、Siemens EDA
🛠️ Tech Stack
EDASynthesisPlace & RouteSTADRC/LVSIR DropPDKSignoff
💼 Roles & Salary
Physical Design Engineer、Timing/Signoff Engineer、EDA Software Engineer、PDK Engineer、CAD Flow Engineer
💰 $180K - $390K / year (EDA / Physical Design) | ¥450K - ¥1.2M / year
📚 Prerequisites: VLSI Physical Design • Static Timing Analysis (STA) • Tcl/Python Scripting • DRC/LVS Rule Decks
Silicon IP, Frontend Verification & Multiphysics
High-speed SerDes/D2D interface IP, ARM/RISC-V CPU IP, UVM testbenches, formal property verification (SVA), DFT/ATPG scan insertion, and SI/PI electromagnetic/thermal multiphysics co-simulation.
🏢 Companies
Arm、Synopsys、Cadence、Rambus、SiFive、Siemens EDA
🛠️ Tech Stack
Silicon IPSerDes IPUVMFormal VerificationDFTATPGSI/PIMultiphysics Simulation
💼 Roles & Salary
Design Verification Engineer、Formal Verification Engineer、DFT Engineer、SI/PI Engineer
💰 $190K - $410K / year (Silicon IP & DV) | ¥500K - ¥1.3M / year
📚 Prerequisites: SystemVerilog & UVM Methodology • SystemVerilog Assertions (SVA) • DFT & Scan Chain Insertion • Signal & Power Integrity (SI/PI)