1.1
1.1 Compute Silicon Architecture & Custom Accelerators
GPU, CPU, TPU, NPU, custom ASIC, SoC, chiplet architecture, tensor/matrix engines, cache hierarchies, NoC interconnects, and heterogeneous compute.
GPU Microarchitecture & Parallel Compute Cores
Streaming multiprocessors (NVIDIA SM / AMD CU / Intel Xe Core), matrix engines (Tensor Core / Matrix Core), FP8/FP4/INT4 micro-op execution, warp/wavefront schedulers, and high-bandwidth on-chip SRAM.
🏢 Companies
NVIDIA、AMD、Intel、Arm、Qualcomm
🛠️ Tech Stack
GPUTensor CoreSM / CUWarp SchedulingSRAMHeterogeneous ComputeFP8/FP4 PrecisionNoC
💼 Roles & Salary
CPU/GPU/AI Accelerator Architect、Microarchitecture Engineer、RTL Design Engineer、Performance Modeling Engineer
💰 $220K - $480K / year (Silicon Valley Base+Equity) | ¥600K - ¥1.6M / year (China HQ)
📚 Prerequisites: Computer Architecture • Verilog / SystemVerilog HDL • Pipelining & Microarchitecture • Parallel Computing & Simulators
⚡【Mini-Sandbox】FlashAttention Memory Savings
Sequence Length:4,096 tokens
Naive Attention
1,024 MB
O(N²) 显存暴涨
FlashAttention
32 MB
节省 97% 显存 (O(N))
Domain-Specific AI Accelerators & Custom ASIC
Google TPU (Systolic Arrays), AWS Trainium/Inferentia, Groq TSP (deterministic streaming), Cerebras Wafer-Scale Engine, and custom low-power edge/cloud ASIC accelerators.
🏢 Companies
Google、AWS、Broadcom、Marvell、Groq、Tenstorrent、Cerebras、Qualcomm、Arm
🛠️ Tech Stack
TPUNPUCustom ASICSystolic ArraySpatial ArchitectureAI AcceleratorsChipletSoC
💼 Roles & Salary
ASIC Design Engineer、SoC Architect、Design Verification Engineer、AI Compiler Engineer
💰 $200K - $440K / year (ASIC Design Track) | ¥500K - ¥1.4M / year
📚 Prerequisites: Systolic Array Architecture • AXI/AMBA Bus Protocols • UVM Verification Methodology • ASIC Frontend Flow