CUDA C/C++ kernels, OpenAI Triton language, FlashAttention-1/2/3 IO-aware tiling, TensorRT graph compiler, AMD ROCm, and Intel OpenVINO heterogeneous acceleration.
IO-aware tiling, on-chip SRAM online softmax calculation, reducing HBM IO from $O(N^2)$ to $O(N)$ with standard $O(N^2 d)$ FLOPs, warp specialization, and OpenAI Triton kernel programming.
TensorRT/TVM/XLA computational graph optimization, automatic operator fusion, CUTLASS 3.x GEMM templates, AMD ROCm/HIP, Intel OpenVINO, and Roofline bottleneck analysis.